How to make a constraint with implication to be soft constraint

SystemVerilog
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2

In reply to peterjin:

You need a newer tool. This was clarified to be legal in the 1800-2017 LRM. From section 18.5.14 Soft constraints:

class Packet;
  rand bit mode;
  rand int length;
  constraint deflt {
  soft length inside {32,1024};
  soft mode -> length == 1024;
  // Note: soft mode -> {length == 1024;} is not legal syntax,
  // as soft must be followed by an expression
  }
endclass