How to combine sv assertions to submodules of DUT in UVM testbench and able to switch assertions off

UVM
, ,
1

Hi,

I would like to know if possible from “uvm testcase” class to have a path back to the DUT submodules in order to switch off assertions. Because assertions are based on sub-module of DUT, the goal is to switch off assertion depends on the test.

DUT module:
module dut_module(
input wire clk,
input wire reset,
…);
example_module example_module_u
(
.example_clk (clk),
.example_count (count),
.example_enable (enable),
.example_ack (ack)
);
endmodule;

//assertion module
module ust_example_assertions #(parameter parameter1)(
//port declartion for the example module
input wire example_clk,
input wire [parameter1-1:0] example_count,
input wire example_enable,
input wire example_ack);
assert_name: assert property(@(posedge example_clk)!(example_enable && example_ack && example_count > 17’h0_1000))
else
$fatal(1,“FATAL: This transaction is invalid in %m at %0d ps.”, $time);
endmodule:ust_example_assertions

//testbench top:
Bind example_module example_assertions#(.parameter1(parameter1)) inst_assert(.*);

//uvm testcase
class example_test extends uvm_test;
…
task run_phase(uvm_phase phase)
$assertoff(1, path to the DUT submodule) //something similar
endtask
endclass

Thanks,
Chao

2

In reply to cw948:

Use below and check:

bind dut_file assertion_file(.assertion_signal(dut_signal));

First comment the $assertoff and run above, if everything is fine then remove comment.

-Sunils

3

In reply to sunils:

Hi Sunil,

Sorry, it doesn’t work for me. The problem is having $assertoff(0) in the testcase unable to switch off assertions. So I thought by giving direct path to the DUT sub-module might help, but what is the path from uvm testcase to DUT submodule?

Thanks,
Chao

4

In reply to cw948:

The path is hierarchical like given below:

$assertoff(0,tb_top.inst_dut);

There are two arguments, first is zero and secondly we are accessing the dut submodu
le from tb top file. inst_dut is instance fo dut submodule in the tb top file.

–Sunils

5

In reply to sunils:

Don’t use $assertoff() statements. They are messy and require code changes/recompilation to change the testbench behavior.

Instead, you should be using your simulation tool’s method for disabling assertions. Each simulator has a unique way of doing this, so you will need to read your tool’s user manual.

Another option is to put the bind statements in a separate top-level module. You can disable all of the assertions associated with the bind statements by not simulating that module.

6

In reply to sunils:

Hi sunils and cgales,

Thank you for the reply.

But the problem is the verification environment I’m working on is UVM testbench, how can I switch assertions off in testcase class or in testcase class access to testbench top?

Thanks,
Chao

7

In reply to cw948:

There is no restriction, you can use the simulator features to switch off/on the assertions.
Doing this from your UVM testbench/test code is more restrictive.