How to combine sv assertions to submodules of DUT in UVM testbench and able to switch assertions off

UVM
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6

In reply to sunils:

Hi sunils and cgales,

Thank you for the reply.

But the problem is the verification environment I’m working on is UVM testbench, how can I switch assertions off in testcase class or in testcase class access to testbench top?

Thanks,
Chao