How to combine sv assertions to submodules of DUT in UVM testbench and able to switch assertions off

In reply to sunils:

Don’t use $assertoff() statements. They are messy and require code changes/recompilation to change the testbench behavior.

Instead, you should be using your simulation tool’s method for disabling assertions. Each simulator has a unique way of doing this, so you will need to read your tool’s user manual.

Another option is to put the bind statements in a separate top-level module. You can disable all of the assertions associated with the bind statements by not simulating that module.