How to combine sv assertions to submodules of DUT in UVM testbench and able to switch assertions off

UVM
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4

In reply to cw948:

The path is hierarchical like given below:

$assertoff(0,tb_top.inst_dut);

There are two arguments, first is zero and secondly we are accessing the dut submodu
le from tb top file. inst_dut is instance fo dut submodule in the tb top file.

–Sunils