How to combine sv assertions to submodules of DUT in UVM testbench and able to switch assertions off

UVM
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3

In reply to sunils:

Hi Sunil,

Sorry, it doesn’t work for me. The problem is having $assertoff(0) in the testcase unable to switch off assertions. So I thought by giving direct path to the DUT sub-module might help, but what is the path from uvm testcase to DUT submodule?

Thanks,
Chao