Compare objects and find mismatch

SystemVerilog
1

Hi there,
How do I find a print mismatch of particular value when comparing two objects of same class? For example, if I have d1,d2,d3 variables in the class, it is possible that only d1 of two objects mismatches. I only want to print obj1.d1 is mismatching with obj2.d1.

2

Are you using the UVM? It has some helper routines so you can define a do_compare method inside your class:

virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer);
      type(this) rhs_;
      $cast (rhs_, rhs);
      do_compare = 1;
      do_compare &= comparer.compare_field ("d1", d1, rhs_.d1, $bits (d1), UVM_HEX);
      do_compare &= comparer.compare_field ("d2", d2, rhs_.d2, $bits (d2), UVM_HEX);
      do_compare &= comparer.compare_field ("d3", d3, rhs_.d3, $bits (d3), UVM_HEX);
   endfunction : do_compare
3

In reply to dave_59:

Thanks Dave. so what if I do not know about the type of object and hence I also do not know about what are the fields in the class. In the example above you have called compare methods for each field. All I want is to compare each of that class and mismatch an error which says this is the field has mismatch with lhs and rhs having different value.

Adding to the point. Yes I am using UVM and I have used uvm_algorithmic_comparator where we pass before_tx, after_tx, and transformer type. I have implemented the transformer function which returns the after_tx. I want to know how does it print particular field when there is a mismatch. For example if after_tx has a field called data then how does comparator knows about the data field since we have passed only object. because mostly we compare whole objects.

4

In reply to sanketshah:

The object you want to compare needs to have virtual do_compare method. It knows the fields in the object and do_compare gets called by uvm_in_order_class_comparator

See http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_paper/DVCon-2011-Easier-UVM-v3.pdf

5

In reply to dave_59:

Thanks dave and sorry for asking so many questions as I am new to UVM.
Two questions.

  1. In my current test bench setup I do not have implemented do_compare method in my transaction. Then how come comparator prints the field name and mismatch value. In below UVM_INFO how does it has access to cg_data.

UVM_WARNING @ 174600100: uvm_test_top.env.tx_scoreboard_0.inline_comp.comp [Comparator Mismatch] differs from
UVM_INFO @ 174600100: reporter [MISCMP] Miscompare for transformed_data.cg_data: lhs = 'h304 : rhs = 'hfb
UVM_INFO @ 174600100: reporter [MISCMP] 1 Miscompare(s) for object mon_data@58523 vs. transformed_data@45434

  1. As I saw in uvm_in_order_class_comparator, I don’t see any do_compare method getting called from there.
6

In reply to sanketshah:

But I do have uvm_object_utils_begin macro in my transaction. So it is possible that all the default methods are there already. But I am still wondering how they are called from uvm_in_order_class_comparator

7

In reply to sanketshah:

Likely that you are using uvm_field_int macros that would automate the compare implementation. See a relevant blog entry (actually motivated by this thread, done by my team here at CVC): Verification Course Blog | VeriLog Courses | CVC

HTH
Regards
Ajeetha, CVC

8

In reply to dave_59:

hello, dave

what if we are not using UVM, Then how can we achieve this using System Verilog.

9

In reply to jishan_bukhari:

“What if…?” Then you are 10+ years behind in verification technology. To answer your question, I would have to essentially replicate the code in the UVM that has this functionality, which is something that I’m not willing to do.

What I can do is recommend that you adapt UVM in tiny pieces, like you would a utility library, and only use the bare minimum to get the functionality you’re looking for. All you need to do is extend your classes from uvm_object. Then you get immediate access to all its methods without having to adopt the full UVM testbench methodology.