Compare objects and find mismatch

SystemVerilog
5

In reply to dave_59:

Thanks dave and sorry for asking so many questions as I am new to UVM.
Two questions.

  1. In my current test bench setup I do not have implemented do_compare method in my transaction. Then how come comparator prints the field name and mismatch value. In below UVM_INFO how does it has access to cg_data.

UVM_WARNING @ 174600100: uvm_test_top.env.tx_scoreboard_0.inline_comp.comp [Comparator Mismatch] differs from
UVM_INFO @ 174600100: reporter [MISCMP] Miscompare for transformed_data.cg_data: lhs = 'h304 : rhs = 'hfb
UVM_INFO @ 174600100: reporter [MISCMP] 1 Miscompare(s) for object mon_data@58523 vs. transformed_data@45434

  1. As I saw in uvm_in_order_class_comparator, I don’t see any do_compare method getting called from there.