i want to check the clockperiod with sv assertion i tried the above code which you mention the issue is i can see if there is any failure in DVE that failure message occur but on the other side when it suppose to pass at that time i dont see any message of success in DVE ?
what could be the issue any idea ?
this is the code which i am trying and you suggested
To have pass or fail messages, you need the action block. Without an action block, if the assertion fails, the simulator will automatically provide a message. Below is an example with the action block. Note that it is not common to have passed messages.
module freq;
bit clk, rst;
time clk_period = 10ns;
initial forever #5 clk=!clk;
property p_period ( int clk_period);
time current_time;
disable iff (rst)
('1, current_time = $time) |=> (clk_period == ($time - current_time) );
endproperty : p_period
ap_period: assert property(@ (posedge clk) p_period(clk_period))
$display("pass at time %t", $time); else
$display("fail at time %t", $time);
endmodule
// simulation results
run 100ns
# pass at time 15
# pass at time 25
# pass at time 35
# pass at time 45
# pass at time 55
# pass at time 65
# pass at time 75
# pass at time 85
# pass at time 95
In your code, if rst becomes high, assertion is disabled. But is there any way to disable the assertion if rst signal toggles from 0->1 or 1->0 during the evaluation.
I have written a code for frequency checking similiar to below code:
property p_period ( int clk_period,error);
time current_time;
disable iff (rst)
('1, current_time = $time) |=> ((clk_period <= ($time - current_time + error)) && (clk_period >= ($time - current_time -error)));
endproperty : p_period
ap_period: assert property(@ (posedge clk) p_period(clk_period))
$display(“pass at time %t”, $time); else
$display(“fail at time %t”, $time);
when I run the simulation (using VCS 2017), log files show assertion failures for all attempts while in ‘verdi assertion debug mode’ it shows success.
Do you think it is related to tool or the issue with assertion?
In reply to ben@SystemVerilog.us:
Hi Ben, I tried as you said, but still assertion is failing (Now in Verdi is shows failure). In Verdi it shows the value assigned to currenttime vairable is 1 for all attempts.
I have tried with both, real current_time and realtime current_time.
timescale is 1ns/1ps .
this is the code:
Avoid writing large assertions. Thus, instead of one assertion with the if() else() construct, write 2 separate assertions. It also makes debugging faster.
If the assertion is used once, avoid arguments.
Avoid using “real” instead of realtime when dealing with time. Though it is OK, there may be some issues with getting the scales OK.
In this forum we discuss language issues, but not tool issues. Thus, in the future do not name tools. However, you may say something like “One simulation tool gave me this error, but one debugging tool gave this other error”.
Code below procuded pass and failed assertions. Try this code with your tools. Any tool bug should be addressed directly with the tool vendor. http://SystemVerilog.us/vf/check_clk.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, en,rst=0, a, b;
default clocking @(posedge clk);
endclocking
realtime clk_period=20ns, clk_period_1=22ns, error_clk=2ns;
initial forever begin
#10;
if(a) clk=!clk;
else if(b) #3 clk=!clk;
else #1 clk=!clk;
end
initial begin
$timeformat(-9, 1, "ns", 8);
$display("%t", $realtime);
end
property p_period_enf;
realtime current_time;
disable iff (rst)
(!en, current_time = $realtime) |=>
(($realtime - current_time) <= (clk_period + error_clk))
&& (($realtime - current_time) >= (clk_period - error_clk));
endproperty : p_period_enf
ap_period_enf: assert property(p_period_enf);
property p_period_en;
realtime current_time;
disable iff (rst)
(en, current_time = $realtime) |=>
(($realtime - current_time) <= (clk_period_1 + error_clk))
&& (($realtime - current_time) >= (clk_period_1 - error_clk)) ;
endproperty : p_period_en
ap_period_en: assert property(p_period_en);
//ap_perid: assert property();
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a, b, en) with
{ a dist {1'b1:=1, 1'b0:=3};
b dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
