In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for your reply.
I have written a code for frequency checking similiar to below code:
property p_period ( int clk_period,error);
time current_time;
disable iff (rst)
('1, current_time = $time) |=> ((clk_period <= ($time - current_time + error)) && (clk_period >= ($time - current_time -error)));
endproperty : p_period
ap_period: assert property(@ (posedge clk) p_period(clk_period))
$display(“pass at time %t”, $time); else
$display(“fail at time %t”, $time);
when I run the simulation (using VCS 2017), log files show assertion failures for all attempts while in ‘verdi assertion debug mode’ it shows success.
Do you think it is related to tool or the issue with assertion?
thanks
Vineet