To have pass or fail messages, you need the action block. Without an action block, if the assertion fails, the simulator will automatically provide a message. Below is an example with the action block. Note that it is not common to have passed messages.
module freq;
bit clk, rst;
time clk_period = 10ns;
initial forever #5 clk=!clk;
property p_period ( int clk_period);
time current_time;
disable iff (rst)
('1, current_time = $time) |=> (clk_period == ($time - current_time) );
endproperty : p_period
ap_period: assert property(@ (posedge clk) p_period(clk_period))
$display("pass at time %t", $time); else
$display("fail at time %t", $time);
endmodule
// simulation results
run 100ns
# pass at time 15
# pass at time 25
# pass at time 35
# pass at time 45
# pass at time 55
# pass at time 65
# pass at time 75
# pass at time 85
# pass at time 95
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115