Clock period checker with SVA

SystemVerilog
8

In reply to ben@SystemVerilog.us:
Hi Ben, I tried as you said, but still assertion is failing (Now in Verdi is shows failure). In Verdi it shows the value assigned to currenttime vairable is 1 for all attempts.
I have tried with both, real current_time and realtime current_time.
timescale is 1ns/1ps .
this is the code:

property p_period (real clk_period, real clk_period_1,real error_clk); 
    real current_time; 
    disable iff (rst)

      ('1, current_time = $realtime) |=> if(~en)((($realtime - current_time) <= (clk_period + error_clk)) && (($realtime - current_time) >= (clk_period - error_clk)))else if(en) ((($realtime - current_time) <= (clk_period_1 + error_clk)) && (($realtime - current_time) >= (clk_period_1 - error_clk))) ;
    endproperty : p_period

Thanks
Vineet