System verilog assertion to check whether a clock is always zero through out the simulation

SystemVerilog
, ,
1

Hi,

I do came across checking a signal whether it is stable or not on a given clock edge, But How to write an assertion to check whether the clock itself is assigned to zero through out the simulation or not.

Regards,
Praveen

2

In reply to praveen1705:
You’ll need to tune this model to your requirements. Here I understood from your very brief requirement statement that you have a clock, but you want to detect if it is active (i.e., alive) and if it is stuck at 1 or at 0. The key to solving this is the fork join_any construct. If no clk, the non-alive block checks for values and uses immediate assertions.


module m; 
  logic clk; 
  bit alive; 
  initial forever #5 clk = !clk;

  initial forever begin 
    am_alive:  assert (alive==1) else $display("%t NOT ALIVE: clk==", $realtime, clk); // 
     fork
        begin 
            @(posedge clk) alive=1'b1; 
        end

        begin 
            #20 alive=0; 
            am_X: assert (clk==1'b0 ||clk==1'b1) else $display("%t clk==", $realtime, clk); //  is X or Z
            am_1: assert (clk==1'b1) else $display("%t clk==", $realtime, clk);   // is X or 0 or Z
        end        
     join_any
  end 
  

  
//  final procedure executes when simulat
   final
    am_1F: assert (clk==1'b1 && alive==1'b1) else $display("%t FINAL: clk==", $realtime, clk); // 0 X or Z

    initial begin // test pattern 
        #100 clk <= 1'b1;
        #100 clk <= 1'bX; 
        #100 clk <= 1'b0;
        #100 clk <= 1'bZ;
        #100 clk <= 1'b1;
      end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

Actually the problem statement is I have a clk which should be zero through out the simulation, If it goes to high at any point, then I do need to report it as an error.

Regards,
Praveen

4

In reply to praveen1705:

 
always @(posedge clk) begin
  am_1F: assert (0) else $display("%t Error: clk==", $realtime, clk); //

Ben

5

In reply to ben@SystemVerilog.us:

Thanks ben