System verilog assertion to check whether a clock is always zero through out the simulation

SystemVerilog
, ,
2

In reply to praveen1705:
You’ll need to tune this model to your requirements. Here I understood from your very brief requirement statement that you have a clock, but you want to detect if it is active (i.e., alive) and if it is stuck at 1 or at 0. The key to solving this is the fork join_any construct. If no clk, the non-alive block checks for values and uses immediate assertions.


module m; 
  logic clk; 
  bit alive; 
  initial forever #5 clk = !clk;

  initial forever begin 
    am_alive:  assert (alive==1) else $display("%t NOT ALIVE: clk==", $realtime, clk); // 
     fork
        begin 
            @(posedge clk) alive=1'b1; 
        end

        begin 
            #20 alive=0; 
            am_X: assert (clk==1'b0 ||clk==1'b1) else $display("%t clk==", $realtime, clk); //  is X or Z
            am_1: assert (clk==1'b1) else $display("%t clk==", $realtime, clk);   // is X or 0 or Z
        end        
     join_any
  end 
  

  
//  final procedure executes when simulat
   final
    am_1F: assert (clk==1'b1 && alive==1'b1) else $display("%t FINAL: clk==", $realtime, clk); // 0 X or Z

    initial begin // test pattern 
        #100 clk <= 1'b1;
        #100 clk <= 1'bX; 
        #100 clk <= 1'b0;
        #100 clk <= 1'bZ;
        #100 clk <= 1'b1;
      end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: