Can anyone please explain the need for $cast in System Verilog with a good example?
In reply to Shri Ganesh:
class parent;
endclass
class child extends parent;
endclass
parent parent_h;
child child1_h;
child child2_h;
child1_h = new();
parent_h = child1_h;
$cast(child2_h, parent_h); // checking if parent_h points to an object of child
// if yse, then assign to child2 handle
// if no, you see error
check oop class if you need
https://verificationacademy.com/courses/systemverilog-oop-for-uvm-verification
In reply to javatea:
Hi,
In the above example, can you please let me know what this statement does?
“parent_h = child1_h”
My assumption is that the parent handle is been replaced by a handle pointing to the child properties and functions. And so, I can use the parent handle to access the child’s properties.
Am I right?
In reply to Shri Ganesh:
child1_h = new(); // create a child object
parent_h = child1_h; // a parent handle points to a child object
nothing special.
try to understand class inheritance and oop if you got more questions.
In reply to javatea:
class cast_parent;
int a;
task sett (int b);
a= b;
$display(“A inside class: %d”, a);
endtask : sett
task print;
$display(“A inside class: %d”, a);
endtask :print
endclass : cast_parent
class cast_child extends cast_parent;
int a = 70000;
task sett (int b);
a= b;
$display(“A inside class: %d”, a);
$display(“B inside class: %d”, b);
endtask : sett
task print;
$display(“MGR inside class: %d”, a);
endtask : print
endclass : cast_child
module test;
cast_parent one;
cast_child two;
initial
begin
one = new();
two = new();
one = two;
one.sett(1001);
one.print;
end
endmodule : test
In the above module, after I have assigned my child handle to parent’s handle, I called the task print via parent’s handle - expecting the printing of the statement - MGR inside class: from the child’s class, while the output I got was from the Parent class.
Please clarify.
In reply to sharat:
Yes, that’s polymorphism.
I am pretty curious to know what happens when we don’t declare the key word virtual and assign the child’s handle to parent’s handle.
child1_h = new(); // create a child object
parent_h = child1_h; // a parent handle points to a child object
Here, parent_h points to parent’s object.
child1_h holds the address to child’s object.
When I assign just like that without “VIRTUAL” keyword, why can’t I access child’s properties?
If I am not able to access the child’s properties without “Virtual” keyword, what’s the need for this statement parent_h = child1_h;
Please explain.
In reply to Shri Ganesh:
https://verificationacademy.com/courses/systemverilog-oop-for-uvm-verification
if you wanna know more, google “compiler” it might help you
In reply to javatea:
But, this a general query OOPs query for which I am not able to find the answers. I am not interested in UVM as of now.
If you guys know, please share it.
In reply to Shri Ganesh:
do you check that link??? whats inside?
if you are not able to find the answer.
I highly recommend you take this chance to start.
I am 100% sure you can find it.
if not, I suggest you drop this course.
In reply to Shri Ganesh:
In reply to javatea:
But, this a general query OOPs query for which I am not able to find the answers. I am not interested in UVM as of now.
If you guys know, please share it.
My SystemVerilog OOP course does not discuss the UVM. It provides you with the OOP basics needed to understand the UVM base class library, or any class based testbench you would like to use or construct yourself.
In reply to Shri Ganesh:
“If I am not able to access the child’s properties without “Virtual” keyword, what’s the need for this statement parent_h = child1_h;”
I have been always feel puzzled about this, are you clear with this now? Could you please explain it to me? Or the example given to us is just to show that if no “virtual” keyword for methods, even a parent handle who was pointed to child object still can not see the child’s overridden methods? can you give me some examples where this is used in UVM library to help me better understand this?