Need for the $cast task in System Verilog

SystemVerilog
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3

In reply to javatea:

Hi,

In the above example, can you please let me know what this statement does?

“parent_h = child1_h”

My assumption is that the parent handle is been replaced by a handle pointing to the child properties and functions. And so, I can use the parent handle to access the child’s properties.
Am I right?