Need for the $cast task in System Verilog

In reply to Shri Ganesh:


class parent; 
endclass

class child extends parent;
endclass

parent parent_h;
child child1_h; 
child child2_h;

child1_h = new();
parent_h = child1_h;

$cast(child2_h, parent_h); // checking if parent_h points to an object of child
                           // if yse, then assign to child2 handle
                           // if no, you see error
                     

check oop class if you need
https://verificationacademy.com/courses/systemverilog-oop-for-uvm-verification