Need for the $cast task in System Verilog

In reply to javatea:

class cast_parent;
int a;

task sett (int b);
a= b;
$display(“A inside class: %d”, a);
endtask : sett

task print;
$display(“A inside class: %d”, a);
endtask :print

endclass : cast_parent

class cast_child extends cast_parent;

int a = 70000;

task sett (int b);
a= b;
$display(“A inside class: %d”, a);
$display(“B inside class: %d”, b);
endtask : sett

task print;
$display(“MGR inside class: %d”, a);
endtask : print

endclass : cast_child

module test;
cast_parent one;
cast_child two;

initial
begin
one = new();
two = new();
one = two;
one.sett(1001);
one.print;
end

endmodule : test

In the above module, after I have assigned my child handle to parent’s handle, I called the task print via parent’s handle - expecting the printing of the statement - MGR inside class: from the child’s class, while the output I got was from the Parent class.

Please clarify.