Need for the $cast task in System Verilog

In reply to Shri Ganesh:

“If I am not able to access the child’s properties without “Virtual” keyword, what’s the need for this statement parent_h = child1_h;”

I have been always feel puzzled about this, are you clear with this now? Could you please explain it to me? Or the example given to us is just to show that if no “virtual” keyword for methods, even a parent handle who was pointed to child object still can not see the child’s overridden methods? can you give me some examples where this is used in UVM library to help me better understand this?