Need for the $cast task in System Verilog

In reply to sharat:

Yes, that’s polymorphism.

I am pretty curious to know what happens when we don’t declare the key word virtual and assign the child’s handle to parent’s handle.

child1_h = new(); // create a child object
parent_h = child1_h; // a parent handle points to a child object

Here, parent_h points to parent’s object.
child1_h holds the address to child’s object.

When I assign just like that without “VIRTUAL” keyword, why can’t I access child’s properties?
If I am not able to access the child’s properties without “Virtual” keyword, what’s the need for this statement parent_h = child1_h;

Please explain.