In reply to MayurKubavat:
Looks like your issue is that the path to the assertion label is not complete.
// CHANGE FROM
$assertkill(0, uvm_test_top.env.scoreboard.assertion_name);
// TO the fix
$assertkill(0, uvm_test_top.env.scoreboard.task_name.assertion_name);
Below is an example that ran OK
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a, b;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
class C;
bit d=1;
task t();
a_intask: assert(d);
endtask
endclass : C
C c;
initial c=new();
always @(posedge clk) begin : alw1
c.d=b;
c.t();
a_intop: assert(b);
if(a) $assertkill(0, top.alw1.a_intop);
if(a) $assertkill(0, top.c.t.a_intask);
end : alw1
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a, b) with
{ a dist {1'b1:=1, 1'b0:=3};
b dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
http://cvcblr.com/home
*
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
*
Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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