How to disable immediate assertions inside class?

SystemVerilog
,
4

In reply to MayurKubavat:

One can add some glue logic to disable the assertion instead of depending on hierarchy of assertions. One can make use of a guarding criteria for assertion to fire. Here is a sample code that works for all the simulators.

Note that you can modify the assert_guard to static or a function. Or you can pass it to the macro input argument, depending on the requirement.

`define ASSERT(VAL,ERR) \
  assert(!assert_guard || (VAL))  else begin \
    $error(ERR); \
end \
  
   
   class A;
      bit assert_guard = 1; // assertion ON by default
      bit a = 0;

      task checkA;
         #10ns;
        CHECK: `ASSERT(a == 1,"Check on A failed") 
      endtask
   endclass

   initial begin
     A Ah = new();
     //$assertoff(0, test.Ah.checkA.CHECK);
     Ah.assert_guard = 0;
     Ah.checkA();
    end
endmodule //test

Moreover, one can use disable statement as for deffered assertions, but that would need exact time for assertion to fire.