How to disable immediate assertions inside class?

SystemVerilog
,
3

I have tried this in different simulators. But it does not work :(

My Code:

module test();
   
   class A;
      bit a = 0;

      task checkA;
      begin
         #10ns;
        CHECK: assert(a == 1) 
          $display($time, "Check on A passed"); 
        else
          $display($time, "Check on A failed");
      end
      endtask
   endclass

	initial
	begin
      A Ah = new();

      $assertoff(0, test.Ah.checkA.CHECK);
      Ah.checkA();

      #10 $finish;
	end

endmodule //test