How to disable immediate assertions inside class?

SystemVerilog
,
5

In reply to sharvil111:
The issue is


# KERNEL: Warning: test.Ah.checkA.CHECK is not a valid $assertoff task parameter.
# KERNEL: Warning: test.checkB.CHECKB is not a valid $assertoff task parameter.
// Use this instead
      $assertoff(0, test.A.CHECK);
      $assertoff(0, test.CHECKB);
 


// Code your testbench here
// or browse Examples
module test();
   bit b=0;
   class A;
      bit a = 0;

     task checkA;
      begin
         #10ns;
        CHECK: assert(a == 1) 
          $display($time, "Check on A passed"); 
        else
          $display($time, "Check on A failed");
      end
      endtask
   endclass
  
    task checkB;
      begin : BB
         #10ns;
        CHECKB: assert(b == 1) 
          $display($time, "CheckB on A passed"); 
        else
          $display($time, "CheckB on A failed");
     end
    endtask

	initial 
	begin : init0
      A Ah = new();
   	
      $assertoff(0, test.A.CHECK);
      $assertoff(0, test.CHECKB);
     
      Ah.checkA();
      checkB(); 	

      #10 $finish;
	end

endmodule //test

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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