`define macros usage

SystemVerilog
1

Can i use ifdef in a macro defination , ex-

define xyz \ assign x = 1;\ ifdef SAMPLE_SWITCH \ assign z = 0;\ else
assign z= 1;
`endif \

Thanks
Vikram dadwal

2

Yes you can. But note that the `ifdef is not evaluated in the declaration of the macro; it is evaluated when the macro is called and expanded.

3

In reply to dave_59:

Alright thanks,
I was looking into code and it is using parametreized macros . And there is a statement like this :

`define xyz(I,R)
assign abc(I).clk = R.duI_clk_x;

so my question is : what does the after the parameter mean ? I understand thatR is a parameter declaration but what does R mean ?

Thanks
Vikram

4

In reply to vdadwal:

I prefer to use the term macro argument. A parameter is something else in Verilog.

In the macro, R by itself is the argument that gets substituted. R is not needed.

However, the argument I shows up twice in the body of the macro; first by itself, and then surrounded by I. The `` is a token separator used to build identifiers and strings. Without it, the bare argument I would disappear into an identifier duI_clk_x. You want the macro

`xyz(1,a)

to be replaced with

assign abc(1).clk = a.du1_clk_x;

5

In reply to dave_59:

So you are suggesting the 2nd `` in I or in R has no meaning so if the macro is like this :

`define xyz(I,R)
assign abc(I).clk = R.duI_clk_x;

`xyz(1,a)

will still be :

assign abc(1).clk = a.du1_clk_x;

6

In reply to vdadwal:

No. The macro should be defined as

`define xyz(I,R)\
assign abc[I].clk = R.du``I``_clk_x;

If you have du``I_clk_x;, then the compiler would only see the tokens du and I_clk_x, and not just I.

7

In reply to dave_59:

If you have du``I_clk_x;, then the compiler would only see the tokens du and I_clk_x, and not just I.

So this means if i just use ``I , the expansion of macro `abc(1,a) would be :
assign abc[1] == R.duI_clk_x . Since its not defined as a separate token ??

Both R and I are arguments to the macro so why you say that no R is needed where as I is needed. Is it because the left hand side has no dependency on R or is it because R is not breaking the lexical variable ?

Also i also see some defines as :

define DUNIT_IOSFSB_ME(I) IF_DUNITCTE.ME_if[``I]

So here I is not used, why ?

Sorry for asking so many questions the LRM just has insufficient info on this.

8

In reply to dave_59:

So this means if i just use ``I , the expansion of macro `abc(1,a) would be :
assign abc[1] == R.duI_clk_x . Since its not defined as a separate token ??

Yes, that would be the result.

Both R and I are arguments to the macro so why you say that no R is needed where as I is needed. Is it because the left hand side has no dependency on R or is it because R is not breaking the lexical variable ?

Correct again. What you call a lexical variable is what the compiler calls a token identifier. The compiler grabs text in chunks called tokens, before it knows what the identifier is (variable, typedef, module name). An identifier starts with a letter, followed by any number of alpha-numeric characters, as well as _(underscore). Any other character ends the token.

So here I is not used, why ?

Only [I] is needed because I is surrounded by characters that are not part of token identifiers.

9

In reply to vdadwal:

Ok , Thanks , do you know where i can find more information on macro usage in system verilog online ?

10

In reply to vdadwal:

I was trying to use the conditional operation in the macros , something like this :

define DUNITCTE_SPID_E(I) \ assign DUNITCTE_SPID_I(I).ispid_pm_clk = ``I ? DUNIT.ckddr1xgated_zcm1n00nfw : DUNIT1.ckddr1xgated_zcm1n00nfw;

`DUNITCTE_SPID_E(0)

is this ok to use the argument as the conditional solving operator ?

Thanks
Vikram

11

Hi Dave,

define WB_DUT_U_ASSIGN(phy_i,idx)\ assign b[phy_i] = DUT_PATH.Ilaneidx.a;\

I tried this code as you suggested but idx is still not getting replaced.

Can you please suggest?

Saurabh

12

In reply to saurabh_vlsi:

Works for me in Questa.

`define WB_DUT_U_ASSIGN(phy_i,idx)\
assign b[phy_i] = `DUT_PATH.Ilane``idx``.a;\

`define DUT_PATH $root  
  module top;
   bit [31:0] b;
   `WB_DUT_U_ASSIGN(12,34)
endmodule

expands to

     assign b[12] = $root.Ilane34.a;

Does your file have a *.sv extension? This only works in SystemVerilog

13

In reply to :

Hi Dave,

I think the issue comes when the macros are used with generate loop.

The complete code is :

define WB_DUT_U_ASSIGN(phy_i,idx)\ assign b[phy_i] = DUT_PATH.Ilaneidx.a;\

genvar wb
generate
for(wb=0;wb<8;wb++) begin:wb_a
`WB_DUT_U_ASSIGN(wb,wb)
end
endgenerate

14

In reply to saurabh_vlsi:

Macros are preprocessor directives. There are expanded before parsing any Verilog/SystemVerilog syntax.

15

In reply to dave_59:

So how does [phy_i] is replaced but idx is not?

16

Hi i am trying to concatenate a macro with a string variable. Below is the code:

define VAR_LANE0 8'h0000; //MEMORY is kind of storage memory, defined outside and being included in this file. I am not showing that part class my_class; reg [8*8:0] str_var = "LANE0"; // a string variable which can store max 8 characters. // here it is storing "LANE0" string. bit [7:0] local_var1 = MEMORY[VAR_LANE0];

bit [7:0] local_var2 = MEMORY[`VAR_str_var]; // trying to concatenate the macro with the 
                                             // string. But error is coming.

Any solution please. I want to achieve the VAR_LANE0 by using VAR_str_var, if any other way is there please tell.

17

In reply to birenkumar:

I don’t think you will be able to do mix compiler time defines with run-time variables. There is no space/tab to distinguish between 2 lexical tokens(VAR ,str_var). When you put space the expression will become illegal.

Not sure about your intent in creating a macro so if you can give some info on what you are trying to do then it will help us in providing proper solution.

You can use parameterized macro but you cannot use a variable while calling it.

`define VAR_LANE(x) 8'h``x
bit [7:0] local_var1 = MEMORY[`VAR_LANE(0)];

or 
`define VAR_LANE0 8'h07
`define VAR(x) `VAR_``x

bit [7:0] local_var1 = `VAR(LANE0);
18

In reply to dave_59:

In reply to saurabh_vlsi:
Macros are preprocessor directives. There are expanded before parsing any Verilog/SystemVerilog syntax.

Hi Dave Rich,

so do you mean we cant access macros inside generate ?

Below is my requirement
`define dev_(n) top.n.XXX

generate
genvar i;
for (i=0; i<=31; i=i+1) begin: gen_force
initial
force `dev_(i).zzz = 1’b1;
end
endgenerate

Finally i need to have : when i=0 , top.0.XXX.zzz=1’b1

Here always “i” value is not substituted into dev_(n) , we could see instead of value of i directly variable “i” got replaced into macro . Is this approach is correct ? could you please let me know is there any other approach to achieve my requirement .
Thanks

19

In reply to Naven8:

Hi Naven,

Thanks. I think you have got my point in your 1st example

`define VAR_LANE(x) 8’h``x

bit [7:0] local_var1 = MEMORY[`VAR_LANE(0)];

This issue had raised many days back. I’ll try this at my end, whenever I find that Issue. If I get any doubt, I’ll surely ask you.
Thanks again.

20

Hi Please provide your inputs

Below is my requirement
`define dev_(n) top.n.XXX

generate
genvar i;
for (i=0; i<=31; i=i+1) begin: gen_force
initial
force `dev_(i).zzz = 1’b1;
end
endgenerate

Finally i need to have : when i=0 , top.0.XXX.zzz=1’b1

Here always “i” value is not substituted into dev_(n) , we could see instead of value of i directly variable “i” got replaced into macro . Is this approach is correct ? could you please let me know is there any other approach to achieve my requirement .
Thanks