In reply to dave_59:
In reply to saurabh_vlsi:
Macros are preprocessor directives. There are expanded before parsing any Verilog/SystemVerilog syntax.
Hi Dave Rich,
so do you mean we cant access macros inside generate ?
Below is my requirement
`define dev_(n) top.n.XXX
generate
genvar i;
for (i=0; i<=31; i=i+1) begin: gen_force
initial
force `dev_(i).zzz = 1’b1;
end
endgenerate
Finally i need to have : when i=0 , top.0.XXX.zzz=1’b1
Here always “i” value is not substituted into dev_(n) , we could see instead of value of i directly variable “i” got replaced into macro . Is this approach is correct ? could you please let me know is there any other approach to achieve my requirement .
Thanks