In reply to saurabh_vlsi:
Works for me in Questa.
`define WB_DUT_U_ASSIGN(phy_i,idx)\
assign b[phy_i] = `DUT_PATH.Ilane``idx``.a;\
`define DUT_PATH $root
module top;
bit [31:0] b;
`WB_DUT_U_ASSIGN(12,34)
endmodule
expands to
assign b[12] = $root.Ilane34.a;
Does your file have a *.sv extension? This only works in SystemVerilog