In reply to vdadwal:
I prefer to use the term macro argument. A parameter is something else in Verilog.
In the macro, R by itself is the argument that gets substituted. R is not needed.
However, the argument I shows up twice in the body of the macro; first by itself, and then surrounded by I. The `` is a token separator used to build identifiers and strings. Without it, the bare argument I would disappear into an identifier duI_clk_x. You want the macro
`xyz(1,a)
to be replaced with
assign abc(1).clk = a.du1_clk_x;