`define macros usage

SystemVerilog
3

In reply to dave_59:

Alright thanks,
I was looking into code and it is using parametreized macros . And there is a statement like this :

`define xyz(I,R)
assign abc(I).clk = R.duI_clk_x;

so my question is : what does the after the parameter mean ? I understand thatR is a parameter declaration but what does R mean ?

Thanks
Vikram