`define macros usage

SystemVerilog
21

In reply to kvssrohit: As I said before, macros get expanded as text for any generate processing. `dev_(i) gets expanded as top.i.XXX

The only way to achieve what you want withing SystemVerilog is to restructure your instance names into an array and access them with proper indexing. top[i].

Otherwise there are other macro processing tools that you can use to generate the identifier names you are looking for. But that becomes quite a maintenance headache.

22

In reply to dave_59:

Hi Dave,

Thank you very much for the response .

Could you please provide any snippet how to achieve my requirement with your suggestion . I tried to reproduce at my end but getting into errors.

Sorry to trouble you.

23

In reply to kvssrohit:

genvar i;
for (i=0; i<=31; i=i+1) begin: gen_force
initial
force top[i].zzz = 1'b1;
end
24

In reply to dave_59:

Hi Dave ,

Thanks you for your prompt response .

I have modified the code as below :

module test;
generate
genvar i;
for (i=0; i<1; i=i+1) begin: gen_force
initial
force top[i].zzz = 1’b1;
end
endgenerate
endmodule

module top0;
int zzz;
endmodule

But here i’m facing errors with this coding, could you please correct my understanding ?

25

In reply to kvssrohit:

module test;

genvar i;
for (i=0; i<2; i=i+1) begin: gen_force
initial
force top.d[i].zzz = 1'b1;
end
endmodule

module top;

dut d[0:1] ();

endmodule

module dut;
int zzz;
endmodule
26

In reply to dave_59:

Thank you very much Dave , i’m able to achieve the requirement with your snippet . Thanks once again .