Best way to learn systemVerilog

SystemVerilog
1

I am new to systemVerilog.
What is the best way to learn it (which tutorial do you reccomand )?

2

In reply to saritr:

Best bet is to pick-up some good books - for SV-Testbench I suggest Chris Spear’s book. For SVA - we have co-authored SVA Handbook.

But beyond books, tutorials - best way is to pick-up some plain Verilog RTL and start writing code as you learn the language. FOr instance see the open-source GPU MIAOW and pick-up small blocks, I am guiding several junior engineers doing precisely that here at CVC Bangalore, see some updates at: http://www.go2uvm.org/2016/07/open-source-gpu-decode-block-gets-open-source-go2uvm-test/

Good Luck,

Regards
Srini

3

In reply to Srini @ CVCblr.com:

Thanks!
Do you mean this book:
https://www.amazon.com/SystemVerilog-Verification-Learning-Testbench-Language/dp/0387270361

4

In reply to saritr:

Yes! A great book indeed. I guess Chris is in now with MENT and maybe monitoring this thread :-)

Srini

5

In reply to Srini @ CVCblr.com:

Should I know verilog for this, or it teaches from beginning?

6

In reply to saritr:
It would help to know where you are starting from, and where you expect to be going. Do you know any HDLs already? Any C/C++? What got you interested in SystemVerilog? Are you going to be doing hardware design or verification? UVM? There are a lot of tutorials out there, but most of them are in pieces covering a small subset. I just released a small course on SystemVerilog classes for those preparing to use the UVM with no prior Object Oriented Programming experience.

7

In reply to saritr:
A few points:

  1. SystemVerilog is a language that expresses concurrency and is well adapted to describe the behavior of circuits. Verilog is a subset of SystemVerilog, and really no longer exists since it is incorporated into SystemVerilog.
  2. There is a misconception that knowing the syntax of an HDL (e.g., VHDL or SystemVerilog) is sufficient to do logic design and verification. Logic design and architecture is much more than that. In my book Real Chip Design and Verification Using Verilog and VHDL I demonstrate the various techniques in applying an HDL to do things like an asynchronous FIFO, and the design of a CPU with FSMs and with microcode.
  3. The point being than there is a distinction between knowing the language (e.g., the sntax and its variations) and applying the language to perform a task.
  4. Another aspect of SystemVerilog is verification. Again, SystemVerilog provides several structures to support verification, such as classes, operators, interfaces, and SystemVerilog Assertions (SVA). UVM added a layer of libraries and methodologies to bring commonalities and flexibility.
  5. Thus, UVM and the application of SVA is more than just learnoing the syntax of the language; there is more to the story.
  6. I find that learning by example is the best way; by that, I mean being exposed to lots of examples, and then digging into the details when some syntax or structure is not clear. Babies don’t learn the alphabet before they learn how to speak! Just dig in, and understand the various facets and application of design and verification using SystemVerilog, rather than learning SystemVerilog syntax first and then learn how to apply the language.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
    // For 10% discount, use code 45KJT5GN @ https://www.createspace.com/5810350
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
8

In reply to dave_59:

I don’t have knowledge in VHDL. I learned electric&electronic engineering but afterwards I didn’t work in hardware, though in software. I know c++. I’m going to do at first verification, and after some time design. I have to learn also UVM (I have already started to read about it, but it will be better to learn systemVerilog at least at the same time.

9

In reply to saritr:

As Dave said you need to know what is driving you .Are you going to be involved in hardware design or verification task?

I suggest you start with Verilog first, design small circuits with minimum function, write testbench and it will better if you have an FPGA Board to play with.
I suggest this book: "FPGA PROTOTYPING BY VERILOG EXAMPLES " (Pong P. Chu 2008),very helpful for the beginners (with the digital circuits design knowledge).

After you get the good foundation in HDLs you can then start with SystemVerilog.
There are a lot of books and tutorial out there. If you want to focus on verification I suggest you start with systemverilog assertion (SVA)

I suggest this book: “A Practical Guide for SystemVerilog Assertions” by Srikanth Vijayaraghavan and Meyyappan Ramanathan. This book is like a tutorial rich in examples to
demonstrate SVA language constructs. I hope this can be helpful for you.

10

In reply to saritr:

In reply to dave_59:
I don’t have knowledge in VHDL. I learned electric&electronic engineering but afterwards I didn’t work in hardware, though in software. I know c++. I’m going to do at first verification, and after some time design. I have to learn also UVM (I have already started to read about it, but it will be better to learn systemVerilog at least at the same time.

  1. Several users use C++ for design and verification, as it is much faster than simulators with SystemVerilog.
  2. Verilog is a subset of SystemVerilog, you can study Verilog concepts, but use the SystemVerilog types of interface (e.g., module declaration, always_ff, always_comb, …).
  3. This may sound very odd, coming from me, but if your strength is really in software, you may want to consider enhancing your career in software. Jobs in Java, cloud computing, and networks are much better paying jobs than jobs in the hardware field. IBM leaned that the hard way when they gave the software to Microsoft!!!

Ben

11

In reply to ben@SystemVerilog.us:

  1. I already work, and in my company they use SystemVerilog for verification.
  2. The question if if there is some guide for systemVerilog which doesn’t assume that I have knoeledge in verilog.
  3. Most of my knowledge in software is in the field of front end (javascript and etc). I never had the chance to work in hardware, and when I got the offer from my company I couldn’t refuse…I have to try, and if not now when?! In my country hardware are not less paying jobs than jobs in software, so it’s ok:)
12

In reply to saritr:

In reply to ben@SystemVerilog.us:

  1. I already work, and in my company they use SystemVerilog for verification.

  2. The question if if there is some guide for systemVerilog which doesn’t assume that I have knoeledge in verilog.

  3. Most of my knowledge in software is in the field of front end (javascript and etc). I never had the chance to work in hardware, and when I got the offer from my company I couldn’t refuse…I have to try, and if not now when?! In my country hardware are not less paying jobs than jobs in software, so it’s ok:)

  4. I like your enthusiasm! Your experience in Java and software will allow you a relatively easy transfer into the verification field of hardware design using SystemVerilog.

  5. The field of verification includes understanding the design requirements (independently of the implementation) and then ,for simulation, write an environment that drives the model with various meaningful tests and verify that the design does meet those requirements. A coverage of what was tested is also needed.

  6. Again, SystemVerilog is just a language that matured from its original base, Verilog. It is compatible with Verilog, but since SystemVerilog envelops Verilog, there is no more Verilog. When people say “Verilog”, they mean that low level subset, and some companies have stuck to this lower level subset.

  7. Aside from books and having the 1800 documentation (free), the best way to learn SystemVerilog with its clauses on SVA and checkers, and with the UVM library is to be mentored.

  8. For mentoring, training classes are essential, and your company should pay for it, as it is to their benefits. If the company refuses to give you this training, then you’re not working for the right company.

  9. For India, I strongly recommend http://cvcblr.com/ for such training. I have known Srini and Ajeetha who head this company for over 12 years. I appreciate Srini’s experience at Intel as a design and verification engr; at Synopys as an application engineer exposed to many of customers’ application issues; an entrepreneur in creating a business in both training and consulting services; as an innovator in creating new products; as contributor to various seminars (e.g., DVCON, DAC, etc); as a co-author who added value with his broad knowledge and experience.

  10. I also recommend that you attend conferences, such as DvCon. At the upcoming 2016 Design & Verification Conference (DvCon India) Srini will present the paper “Verify thy Verifier via SVUnit”

  11. There are many papers freely available on the topic of using SystemVerilog, Some sites I recommend include

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
    // For 10% discount, use code 45KJT5GN @ https://www.createspace.com/5810350
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
13

In reply to ben@SystemVerilog.us:

Thanks Ben.
I’m not from India so unfortantly your reccomendations doesn’t help me. Are you familiar with similar training/courses in Israel?:)

14

In reply to saritr:

In reply to ben@SystemVerilog.us:
I’m not from India so unfortunately your recommendations doesn’t help me. Are you familiar with similar training/courses in Israel?:)

  1. India is unique in the need/acceptance for this type of mentoring/incubation training for those who are about to enter the real working field. This is because there are many college graduates, and companies want to hire experienced engrs.
  2. What other countries have done is hire training companies to provide in-house training for a very limited duration.

  3. I know c++. I’m going to do at first verification, and after some time design. I have to learn also UVM (I have already started to read about it, but it will be better to learn systemVerilog at least at the same time.

  • 4. In your case, the best way to learn SystemVerilog is to start with verification at the black box level, rather than design level. This is because design involves knowing various design techniques and approaches, and you’re not there yet. At the black box verification level, you’re looking at the requirements and evaluate the design responses to those requirements. I believe that assertions is also keyed to the verification.
    5. As I previously mentioned, there are many sites that provide free training and papers on UVM and on SystemVerilog. These examples will give you plenty of “exposure”, and for structures that you don’t understand, look them up.
    6. Your company should provide some training for you, and they should also team you up with other engrs for mentoring you when you need quick responses and guidance. I played that role of mentoring when engrs were unsure about application of the language.
    7. A word of caution: Be very wary that you are not setup into a situation for failure, and that mgt is using that failure as an excuse for firing you. I’ve seen this done many times! This is because for “political” reasons a company may not fire someone without cause, and thus a cause is created. That may not be the case for you, but be careful, a word of sincere advice.
    8. Israel is a country that is very very strong in the technical field. I strongly believe that software, along with cloud computing and networking is growing at a faster pace than hardware. Engrs in sw do get paid more than engrs in hdwre; something to consider, at least as an alternate.

Ben Cohen ben@systemverilog.us
http://www.systemverilog.us/

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
    // For 10% discount, use code 45KJT5GN @ https://www.createspace.com/5810350
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115