Best way to learn systemVerilog

SystemVerilog
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In reply to saritr:

In reply to dave_59:
I don’t have knowledge in VHDL. I learned electric&electronic engineering but afterwards I didn’t work in hardware, though in software. I know c++. I’m going to do at first verification, and after some time design. I have to learn also UVM (I have already started to read about it, but it will be better to learn systemVerilog at least at the same time.

  1. Several users use C++ for design and verification, as it is much faster than simulators with SystemVerilog.
  2. Verilog is a subset of SystemVerilog, you can study Verilog concepts, but use the SystemVerilog types of interface (e.g., module declaration, always_ff, always_comb, …).
  3. This may sound very odd, coming from me, but if your strength is really in software, you may want to consider enhancing your career in software. Jobs in Java, cloud computing, and networks are much better paying jobs than jobs in the hardware field. IBM leaned that the hard way when they gave the software to Microsoft!!!

Ben