Best way to learn systemVerilog

In reply to saritr:

As Dave said you need to know what is driving you .Are you going to be involved in hardware design or verification task?

I suggest you start with Verilog first, design small circuits with minimum function, write testbench and it will better if you have an FPGA Board to play with.
I suggest this book: "FPGA PROTOTYPING BY VERILOG EXAMPLES " (Pong P. Chu 2008),very helpful for the beginners (with the digital circuits design knowledge).

After you get the good foundation in HDLs you can then start with SystemVerilog.
There are a lot of books and tutorial out there. If you want to focus on verification I suggest you start with systemverilog assertion (SVA)

I suggest this book: “A Practical Guide for SystemVerilog Assertions” by Srikanth Vijayaraghavan and Meyyappan Ramanathan. This book is like a tutorial rich in examples to
demonstrate SVA language constructs. I hope this can be helpful for you.