Best way to learn systemVerilog

SystemVerilog
7

In reply to saritr:
A few points:

  1. SystemVerilog is a language that expresses concurrency and is well adapted to describe the behavior of circuits. Verilog is a subset of SystemVerilog, and really no longer exists since it is incorporated into SystemVerilog.
  2. There is a misconception that knowing the syntax of an HDL (e.g., VHDL or SystemVerilog) is sufficient to do logic design and verification. Logic design and architecture is much more than that. In my book Real Chip Design and Verification Using Verilog and VHDL I demonstrate the various techniques in applying an HDL to do things like an asynchronous FIFO, and the design of a CPU with FSMs and with microcode.
  3. The point being than there is a distinction between knowing the language (e.g., the sntax and its variations) and applying the language to perform a task.
  4. Another aspect of SystemVerilog is verification. Again, SystemVerilog provides several structures to support verification, such as classes, operators, interfaces, and SystemVerilog Assertions (SVA). UVM added a layer of libraries and methodologies to bring commonalities and flexibility.
  5. Thus, UVM and the application of SVA is more than just learnoing the syntax of the language; there is more to the story.
  6. I find that learning by example is the best way; by that, I mean being exposed to lots of examples, and then digging into the details when some syntax or structure is not clear. Babies don’t learn the alphabet before they learn how to speak! Just dig in, and understand the various facets and application of design and verification using SystemVerilog, rather than learning SystemVerilog syntax first and then learn how to apply the language.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
    // For 10% discount, use code 45KJT5GN @ https://www.createspace.com/5810350
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115