In reply to saritr:
It would help to know where you are starting from, and where you expect to be going. Do you know any HDLs already? Any C/C++? What got you interested in SystemVerilog? Are you going to be doing hardware design or verification? UVM? There are a lot of tutorials out there, but most of them are in pieces covering a small subset. I just released a small course on SystemVerilog classes for those preparing to use the UVM with no prior Object Oriented Programming experience.