I am trying to write assertion to check clock gating feature.
Whenever my clk_gate_cfg is 0 my clk will stop after 2:3 cycle for the particular block and will remain stop/zero till clk_gate_cfg will not assert.
Like in my env i have reg "clk_gate_cfg" .It has 8 bit register.
I have wrote below assertion for the above requirement. Please let me know where i am doing wrong.
This assertion is passing in every cases.
((top_th.abc.abc_core.cfg_reg.clk_gate_cfg == 0) ##[2:3] (!top_th.abc.abc_core.trif_core.clk_i)) |-> top_th.abc.abc_core.trif_core.clk_i ==0 throughout (top_th.abc.abc_core.cfg_reg.clk_gate_cfg==1)[->1]