Assertion on clock gating

SystemVerilog
,
2

In reply to kuldeep sharma:
I see your requirements as:


//Whenever my clk_gate_cfg is 0 my clk will stop after 2:3 cycle 
// for the particular block and will remain stop/zero till clk_gate_cfg will not assert.

// Like in my env i have reg "clk_gate_cfg" .It has 8 bit register.
property clk_gating
@(posedge top_th.ref_clk)
  $fell(top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1]) |->   
  ##[2:3] top_th.abc.abc_core.trif_core[1].clk_i ==0 [*1:$] intersect 
                (top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1]==1)[->1];
endproperty

Ben Cohen
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