Assertion on clock gating

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for the reply. I have few queries.

How many times Assertion print will come ?
Or Will it come when "clk_gate_cfg[1]==1) ?
Above assertion is not failing when i am doing clock disable for fist bit and checking clock for another block .In my desgin 1 bit is gating clock for 1 instance of core. Like

property clk_gating
@(posedge top_th.ref_clk)
fell(top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1]) |-> ##[2:3] top_th.abc.abc_core.trif_core[2].clk_i ==0 [*1:] intersect
(top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1]==1)[->1];
endproperty