Assertion on clock gating

SystemVerilog
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4

In reply to kuldeep sharma:
I went overboard on the use of the intersect


 // !a[*1:$] intersect a[->1] should fail
 // !a[*1:$] ##1 a intersect a[->1] // ok
  // but then you don't need the intersect 
$fell(top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1]) |->   
  ##[2:3] top_th.abc.abc_core.trif_core[1].clk_i ==0 [*1:$] ##1
                (top_th.abc.abc_core.cfg_reg.clk_gate_cfg[1];

Clarify your comments