In reply to davidct:
It looks to me that your issue is that the model that Srini provided is more of a template, and the body of that template needs to be complete.
// The body of that
import reg_slice_pkg::*;
class reg_slice_xactn extends uvm_sequence_item;
`uvm_object_utils_begin(reg_slice_xactn)
`uvm_object_utils_end
extern function new(string name="reg_slice_xactn");
endclass : reg_slice_xactn
// The body of that external function needs to be filled
function reg_slice_xactn::new(string name="reg_slice_xactn");
super.new(name);
endfunction : new
Below is an example of a driver I did a few years ago for a loadable counter.
If I were to redo this, I would use the current Srini’s guidelines.
Again, this is an old model, but it may guide you in the right directions.
`ifndef COUNTER_DRIVER
`define COUNTER_DRIVER
// /UVM_counter_with_resp0/tb_src/counter_driver.sv
class counter_driver extends uvm_driver #(counter_xactn, counter_xactn);
string tID;
virtual interface counter_if.drvr_if_mp vif;
//counter_xactn req; is already in uvm_driver
counter_xactn item_copy; // for debug
bit[3:0] ct; // used as a test case in the response
function new(string name, uvm_component parent);
super.new(name,parent);
enable_stop_interrupt = 1;
tID=get_type_name();
tID=tID.toupper();
// item_copy=new();
item_copy=counter_xactn::type_id::create("item_copy", this);
endfunction : new
`uvm_component_utils_begin(counter_driver)
`uvm_field_object(req, UVM_ALL_ON)
`uvm_component_utils_end
task get_and_drive();
counter_xactn t; // to hold gotten item as a copy, keeping original pristine
// rsp=new();
rsp=counter_xactn::type_id::create("rsp", this); // not needed in this case
forever
begin
//wait(vif.reset==0); //block until reset released
seq_item_port.get_next_item(req); // New item at every call, cannot view this
$cast(t, req);
$display("--****************--");
send_to_dut(t);
rsp.set_id_info(req); // Copies the sequence_id and transaction_id
// from the referenced item (req) into the calling item (rsp)
rsp.data = ct+1'b1; //
ct++;
seq_item_port.put_response(rsp);
seq_item_port.item_done();
end
endtask : get_and_drive
// copy elements of item into item_copy
function void copy_items(counter_xactn dest, counter_xactn src);
dest.kind=src.kind;
dest.data=src.data;
dest.ld=src.ld;
dest.rst_n=src.rst_n;
dest.reset_cycles=src.reset_cycles;
dest.idle_cycles=src.idle_cycles;
endfunction : copy_items
task send_to_dut(input counter_xactn item);
uvm_report_info(tID,$psprintf("%s : item sent is %0s",tID,item.sprint()),UVM_MEDIUM);
copy_items(item_copy, item); // Do this for viewing in waveform view
this.vif.driver_cb.kind_cp<=item.kind; // put into interface for debug
case(item.kind)
CT_LOAD : begin
this.load_task(item.data);
end
CT_RESET : begin
this.reset_task(1, item);
end
CT_WAIT : begin
this.idle_task(item.data);
end
CT_DONE : begin
this.done_task(item);
end
endcase
endtask : send_to_dut
task run();
fork
begin
// uvm_default_printer = uvm_default_line_printer;
// uvm_default_printer=new(); // << error
uvm_report_info(tID,$psprintf(" %s : running",tID),UVM_MEDIUM);
end
begin
//reset_dut(); //fill in "reset_dut()" if needed
get_and_drive();
end
join
endtask : run
virtual function void report();
//fill in any reporting code if needed
logic dummy;
endfunction : report
task load_task(int data);
this.vif.driver_cb.data_in <= data;
this.vif.driver_cb.rst_n <= 1'b1;
this.vif.driver_cb.ld <= 1'b1;
@(this.vif.driver_cb)this.vif.driver_cb.ld <= 1'b0;
endtask : load_task
// reset
task reset_task(int r,counter_xactn req);
automatic logic[3:0] v;
this.vif.driver_cb.ld <= 1'b0;
// Line below not working in NC
// if (!randomize(v)) `uvm_error("MYERR", "This is a randomize error");
// ap_rand01: assert(randomize(v));
// this.vif.driver_cb.data_in <= v; // for random numbers in data_in
this.vif.driver_cb.data_in <= req.data;
repeat(r) this.vif.driver_cb.rst_n <= 1'b0;
// @(this.vif.driver_cb);
@(this.vif.driver_cb)this.vif.driver_cb.rst_n <= 1'b1;
// @(this.vif.driver_cb);
endtask : reset_task
// IDLE
task idle_task(int data);// for now, make idle for 4 cycles
logic[3:0] v=data;
this.vif.driver_cb.rst_n <= 1'b1;
this.vif.driver_cb.ld <= 1'b0;
this.vif.driver_cb.data_in <= data;
@(this.vif.driver_cb);
// for (int i=0; i<1; i++) begin
// this.vif.driver_cb.ld <= 1'b0;
// ap_rand01: assert(randomize(v));
// this.vif.driver_cb.data_in <= v;
// @(this.vif.driver_cb);
// end
endtask : idle_task
// DONE, for now, a do nothing
task done_task(counter_xactn req);
this.vif.driver_cb.data_in <= req.data;
this.vif.driver_cb.rst_n <= 1'b1;
this.vif.driver_cb.ld <= 1'b0;
@(this.vif.driver_cb);
endtask : done_task
endclass : counter_driver
`endif
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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