Example uvm testbench for a simple rtl such as register slice

In reply to davidct:

David, pleasee believe me. It is useless what you are doing. This way you’ll never understand the UVM.
My recommendation is to start with an education step. The Verification Academy is offering great material. See here
https://verificationacademy.com/courses/introduction-to-the-uvm and
Basic UVM | Universal Verification Methodology | Verification Academy

You can use the code template to experience your Knowledge.