In reply to davidct:
FYI, I put “task pre_body” and “task post_body” in seq_tests/reg_slice_rand_seq.sv
task pre_body();
uvm_report_info(get_full_name(),“pre_body() callback”, UVM_MEDIUM);
endtask: pre_body
task post_body();
uvm_report_info(get_full_name(),“post_body() callback”, UVM_MEDIUM);
endtask: post_body
and I can see the uvm report display the text :
UVM_INFO …/tb_src/reg_slice_scoreboard.sv(24) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_scoreboard_0 [reg_slice_scoreboard_0] Start of Run phase …
UVM_INFO …/tb_src/reg_slice_output_monitor.sv(27) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_output_monitor_0 [reg_slice_output_monitor_0] Run Phase is Running …
UVM_INFO …/tb_src/reg_slice_input_monitor.sv(27) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_input_monitor_0 [reg_slice_input_monitor_0] Run Phase is Running …
UVM_INFO …/tb_src/reg_slice_driver.sv(30) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_driver_0 [reg_slice_driver_0] Start of Reset Phase …
UVM_INFO …/tb_src/reg_slice_driver.sv(34) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_driver_0 [reg_slice_driver_0] End of Reset Phase …
UVM_INFO …/seq_tests/reg_slice_rand_test.sv(19) @ 0: uvm_test_top [uvm_test_top] Test is running…
UVM_INFO …/tb_src/reg_slice_driver.sv(38) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_driver_0 [reg_slice_driver_0] Start of Main Phase …
UVM_INFO @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0@@reg_slice_rand_seq_0 [uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0.reg_slice_rand_seq_0] pre_body() callback
UVM_INFO …/seq_tests/reg_slice_rand_seq.sv(41) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0@@reg_slice_rand_seq_0 [reg_slice_rand_seq_0] :Sequence is Running …
UVM_INFO …/seq_tests/reg_slice_rand_seq.sv(44) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0@@reg_slice_rand_seq_0 [reg_slice_rand_seq_0] :Sequence is Complete …
UVM_INFO @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0@@reg_slice_rand_seq_0 [uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_sequencer_0.reg_slice_rand_seq_0] post_body() callback
UVM_INFO …/seq_tests/reg_slice_rand_test.sv(24) @ 0: uvm_test_top [uvm_test_top] End of main phase in test
UVM_INFO …/tb_src/reg_slice_fcov.sv(36) @ 0: uvm_test_top.reg_slice_env_0.reg_slice_agent_0.reg_slice_fcov_0 [reg_slice_fcov_0] Test achieved functional coverage: 0.00%