Example uvm testbench for a simple rtl such as register slice

UVM
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In reply to ben@SystemVerilog.us:

Thanks Ben for pointing out the file

tb_src/reg_slice_xactn.svh

and some example driver code.

To start with understanding BFM driver,
I’m reading this website that shows 4 use models of a driver
and some simple UVM driver code.

http://www.learnuvmverification.com/index.php/2015/10/03/uvm-driver-use-models-part-2/