Hello I am facing some issues with a clock agent I made .
This agent has a clk interface and runs by a clock_sequence which is started in test.
Now I have two more interfaces in top file viz.
system_interface instance_u0 (.sys_clk (clk_interface.clk ) ,
.sys_rst (clk_interface.rst )) ;
and
rsp_interface instance_u1 (.sys_clk (clk_interface.clk ) ,
.sys_rst (clk_interface.rst)) ;In the above instantiation clk_interface is set (uvm_config_db)in top file itself . Other two interfaces are also set in the top file itself . The other two interfaces need a clk and rst for internal SV clocking blocks. This is not working .
NOW clk_interface is working fine with DUT . clk_seqs provides clock to DUT . But other sequences which is running for other two interfaces and provides other data items to their respective drivers is not working because clock is not inferred in the top file to their interfaces. Any ideas on How to solve this ??
I am open to changing my environment Once I get some clarity on
1) If I use a clk agent . clk's logic is in clk_seqs . SAME clock and rst should be inferred on other two interfaces.
2) Its necessary for me use the same clock agent as their are many clocks with many functionalities in that agent .
3) If I get more information on How to use clock agent properly without a seqs , that is also acceptable .
Thank you . Any help is appreciated.
