UVM clock Agent .

Question

Hello I am facing some issues with a clock agent I made .
This agent has a clk interface and runs by a clock_sequence which is started in test.
Now I have two more interfaces in top file viz.

system_interface instance_u0 (.sys_clk (clk_interface.clk ) ,
                              .sys_rst (clk_interface.rst )) ;

and

rsp_interface  instance_u1 (.sys_clk (clk_interface.clk )  ,
                            .sys_rst (clk_interface.rst)) ;

In the above instantiation clk_interface is set (uvm_config_db)in top file itself . Other two interfaces are also set in the top file itself . The other two interfaces need a clk and rst for internal SV clocking blocks. This is not working .

NOW clk_interface is working fine with DUT . clk_seqs provides clock to DUT . But other sequences which is running for other two interfaces and provides other data items to their respective drivers is not working because clock is not inferred in the top file to their interfaces. Any ideas on How to solve this ??

I am open to changing my environment Once I get some clarity on
1) If I use a clk agent . clk's logic is in clk_seqs . SAME clock and rst should be inferred on other two interfaces.
2) Its necessary for me use the same clock agent as their are many clocks with many functionalities in that agent .
3) If I get more information on How to use clock agent properly without a seqs , that is also acceptable .
Thank you . Any help is appreciated.

Answer 1

chr_sue

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3893 posts

November 27, 2019 at 6:46 am

In reply to sarth21:
In your question I do not understand what you mean with 'In the above instantiation clk_interface is set (uvm_config_db)in top file itself'.
In any way you need an instance of your clock interface like this

sv_clk_interface clk_interface();
Does this exist?

Answer 2

sarth21

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22 posts

November 27, 2019 at 8:03 am

In reply to chr_sue:

Yes it does exist. I meant that clk_interface is set using uvm_config_db in top file and get I'm env - then agent and then in driver. This is done because logic for clock is driven by a sequence. So to satisfy vif.clk <= req.clk.
What I want is the clock which I am giving from a sequence should be inputted in other interfaces (above mentioned).

So clk is reflected in clk_interface and DUT. But not in another interfaces. Same clk is needed in other interfaces as it has SV Clocking blocks.

Answer 3

chr_sue

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3893 posts

November 27, 2019 at 10:47 am

In reply to sarth21:

If the DUT is connected to the clk_interface and it works then the clk_interface should have been connected to all relevant signals. Did you check the waveforms of the clk_interface and the other interfaces?

Answer 4

sarth21

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22 posts

November 28, 2019 at 11:09 pm

In reply to chr_sue:

Hello sir ,
Now the clock falls in the interface .That issue was solved. I didn't instantiated properly . Now I have another issue with clk_sequence .

Following is from clk_sequence code .

  task body();
    REQ req; 
  begin
    req = trans::type_id::create("req");
    start_item(req);
    req.period =      20 ;
    req.phase_shift = '0 ;
    req.init_rst =    '0 ;
    req.init_clk =    '0 ;
    finish_item(req);
  end
endtask

Here I am just giving an initial value for clock and reset . Following is driver code

  task run_phase (uvm_phase phase);
    REQ req ;
   begin
    seq_item_port.get_next_item(req);
    drive_rst(req);
    drive_clk(req);
    seq_item_port.item_done(req);
  end
endtask
 
//Drive clk task 
task drive_clk(REQ req);
begin
 fork
  logic init_clk_value ;
  logic phase_shift    ;
  logic half_period    ;
 
  init_clk_value = req.init_clk    ;
  phase_shift    = req.phase_shift ;
  half_period    = req.period/2  ;
 
  if(phase_shift)begin
    #phase_shift;
  end 
  vif.clk = init_clk_value ;
  forever begin
    vif.clk = #half_period ~vif.clk ;
  end
join_none
end
 
 
//Drive rst task
task drive_rst(REQ req);
begin
  fork
  begin
    logic rst_val ;
    logic init_clk_value ;
 
    init_clk_value = req.init_clk ;
    rst_val        = req.init_rst ;
 
    @(posedge vif.clk)
    #1step;
    vif.rst = rst_val ;
  end
join_none
end
endtask

Now I know forever loop is causing following errors
//Iteration limit reached 10000 at time 0 ns ;
Is there any other way to drive clk and rst properly throughout the simulation ?
But keeping a separate agent for now is necessary.

Answer 5

chr_sue

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3893 posts

November 29, 2019 at 7:31 am

In reply to sarth21:

You are missing at the end of the task drive_clk endtask.

Answer 6

sarth21

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22 posts

December 01, 2019 at 9:32 pm

In reply to chr_sue:

yes . I kept missing "endtask" gives me the same error above.

Answer 7

Solution

sarth21

Full Access

22 posts

December 04, 2019 at 10:10 pm

In reply to chr_sue:

Thank you .The solution was changing Data types from
1) logic to int
2) Running the test in hdl_top itself.

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