Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
UVM
  • Home
  • Forums
  • UVM
  • UVM clock Agent .

UVM clock Agent .

UVM 6753
uvm_agent 5 #systemverilog interface 3 uvm interface 3 uvm_sequence 23
sarth21
sarth21
Full Access
22 posts
November 27, 2019 at 5:25 am

Hello I am facing some issues with a clock agent I made .
This agent has a clk interface and runs by a clock_sequence which is started in test.
Now I have two more interfaces in top file viz.

system_interface instance_u0 (.sys_clk (clk_interface.clk ) ,
                              .sys_rst (clk_interface.rst )) ;

and
rsp_interface  instance_u1 (.sys_clk (clk_interface.clk )  ,
                            .sys_rst (clk_interface.rst)) ;

In the above instantiation clk_interface is set (uvm_config_db)in top file itself . Other two interfaces are also set in the top file itself . The other two interfaces need a clk and rst for internal SV clocking blocks. This is not working .

NOW clk_interface is working fine with DUT . clk_seqs provides clock to DUT . But other sequences which is running for other two interfaces and provides other data items to their respective drivers is not working because clock is not inferred in the top file to their interfaces. Any ideas on How to solve this ??

I am open to changing my environment Once I get some clarity on
1) If I use a clk agent . clk's logic is in clk_seqs . SAME clock and rst should be inferred on other two interfaces.
2) Its necessary for me use the same clock agent as their are many clocks with many functionalities in that agent .
3) If I get more information on How to use clock agent properly without a seqs , that is also acceptable .
Thank you . Any help is appreciated.

Replies

Log In to Reply
chr_sue
chr_sue
Full Access
3893 posts
November 27, 2019 at 6:46 am

In reply to sarth21:
In your question I do not understand what you mean with 'In the above instantiation clk_interface is set (uvm_config_db)in top file itself'.
In any way you need an instance of your clock interface like this

sv_clk_interface clk_interface();
Does this exist?

sarth21
sarth21
Full Access
22 posts
November 27, 2019 at 8:03 am

In reply to chr_sue:

Yes it does exist. I meant that clk_interface is set using uvm_config_db in top file and get I'm env - then agent and then in driver. This is done because logic for clock is driven by a sequence. So to satisfy vif.clk <= req.clk.
What I want is the clock which I am giving from a sequence should be inputted in other interfaces (above mentioned).

So clk is reflected in clk_interface and DUT. But not in another interfaces. Same clk is needed in other interfaces as it has SV Clocking blocks.

chr_sue
chr_sue
Full Access
3893 posts
November 27, 2019 at 10:47 am

In reply to sarth21:

If the DUT is connected to the clk_interface and it works then the clk_interface should have been connected to all relevant signals. Did you check the waveforms of the clk_interface and the other interfaces?

sarth21
sarth21
Full Access
22 posts
November 28, 2019 at 11:09 pm

In reply to chr_sue:

Hello sir ,
Now the clock falls in the interface .That issue was solved. I didn't instantiated properly . Now I have another issue with clk_sequence .

Following is from clk_sequence code .

  task body();
    REQ req; 
  begin
    req = trans::type_id::create("req");
    start_item(req);
    req.period =      20 ;
    req.phase_shift = '0 ;
    req.init_rst =    '0 ;
    req.init_clk =    '0 ;
    finish_item(req);
  end
endtask

Here I am just giving an initial value for clock and reset . Following is driver code

  task run_phase (uvm_phase phase);
    REQ req ;
   begin
    seq_item_port.get_next_item(req);
    drive_rst(req);
    drive_clk(req);
    seq_item_port.item_done(req);
  end
endtask
 
//Drive clk task 
task drive_clk(REQ req);
begin
 fork
  logic init_clk_value ;
  logic phase_shift    ;
  logic half_period    ;
 
  init_clk_value = req.init_clk    ;
  phase_shift    = req.phase_shift ;
  half_period    = req.period/2  ;
 
  if(phase_shift)begin
    #phase_shift;
  end 
  vif.clk = init_clk_value ;
  forever begin
    vif.clk = #half_period ~vif.clk ;
  end
join_none
end
 
 
//Drive rst task
task drive_rst(REQ req);
begin
  fork
  begin
    logic rst_val ;
    logic init_clk_value ;
 
    init_clk_value = req.init_clk ;
    rst_val        = req.init_rst ;
 
    @(posedge vif.clk)
    #1step;
    vif.rst = rst_val ;
  end
join_none
end
endtask

Now I know forever loop is causing following errors
//Iteration limit reached 10000 at time 0 ns ;
Is there any other way to drive clk and rst properly throughout the simulation ?
But keeping a separate agent for now is necessary.

chr_sue
chr_sue
Full Access
3893 posts
November 29, 2019 at 7:31 am

In reply to sarth21:

You are missing at the end of the task drive_clk endtask.

sarth21
sarth21
Full Access
22 posts
December 01, 2019 at 9:32 pm

In reply to chr_sue:

yes . I kept missing "endtask" gives me the same error above.

Solution

Solution

sarth21
sarth21
Full Access
22 posts
December 04, 2019 at 10:10 pm

In reply to chr_sue:

Thank you .The solution was changing Data types from
1) logic to int
2) Running the test in hdl_top itself.

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA