In reply to chr_sue:
Yes it does exist. I meant that clk_interface is set using uvm_config_db in top file and get I’m env - then agent and then in driver. This is done because logic for clock is driven by a sequence. So to satisfy vif.clk <= req.clk.
What I want is the clock which I am giving from a sequence should be inputted in other interfaces (above mentioned).
So clk is reflected in clk_interface and DUT. But not in another interfaces. Same clk is needed in other interfaces as it has SV Clocking blocks.