Topics tagged vcs

Topic	Replies	Views	Activity
Illegal ref port connection error SystemVerilog SystemVerilog , UVM , vcs	1	752	May 24, 2024
Can I Dump perticular protocol singnal using wildcard (*)? How can I Dump input,inout, output signals only? UVM SystemVerilog , UVM , SV , vcs , Dumping , simvision	2	1421	July 11, 2019
Alternative for disable_iff (rst_n==0) in assert proprty SystemVerilog SystemVerilog , assertion , assertion-errors , SVA-Assertion , vcs , Lint	3	2555	October 30, 2016
UVM compilation dependencies UVM UVM , compilation , vcs , dependencies	1	3373	March 22, 2016
Comparing types returned by get_type() UVM UVM , questa , get_type , type-operator , vcs	3	2486	February 4, 2015