Illegal ref port connection error

SystemVerilog
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1

In my code I have a function whose ports are defined like this:
function void func(bit a, ref uvm_reg regs[$], uvm_reg_map map=null);

When I try to compile with a call to the function that looks like this:
func(a, regs);
I get this error:

Error-[IRPC] Illegal ref port connection
{path to file}
$unit, "null"
  Illegal connection to the ref port 'map' of function/task 
  'func',formal argument should
  have same type as actual argument.

If I interpret this correctly, it seems to think that map is passed by reference, which is not my intention. If an argument to a function is declared as ref, does that cause every succeeding argument to be passed by reference? If so, what’s the best way for me to not have map get passed by reference, since I still want it to be an optional argument?

Thank you.

2

According to the LRM what you are observing is true.

Function declarations default to the formal direction input if no direction has been specified. Once a
direction is given, subsequent formals default to the same direction

Page 325 in IEEE1800-2017
Once direction or type of the variable is declared in the formal declaration, the subsequent formal declarations will use the former direction and type.
to fix your issue, try this function declaration:

function void func(bit a, ref uvm_reg regs[$], input uvm_reg_map map=null);

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