Verification Academy

UART

Topic		Replies	Views	Activity
Problem with constructing UART reg model UVM SystemVerilog , UVM , uvm_reg , UART		0	486	June 11, 2022
CRC5 verification - initial/seed CRC value SystemVerilog SystemVerilog , CRC5 , UART		0	1043	December 12, 2021
If my monitor samples some data and if ,based on some conditions i need some signal in the interface to be asserted, how can i do that? UVM UVM , VIP , UART		1	855	April 20, 2020
SystemVerilog "Lock up" on FPGA SystemVerilog SystemVerilog , UART , FPGA		1	1095	March 3, 2020
Stucked at UART formal verification SystemVerilog SystemVerilog , assertion , UART		7	4280	June 17, 2018