Topics tagged sequence

Topic	Replies	Views	Activity
Sending Sequence values through test class UVM UVM , UVM-Sequence-Library , sequence , trasaction , test-class , uvm-trasactio	6	3127	July 16, 2018
Sequence and sequencer interactions in UVM UVM UVM , sequence	4	2280	May 18, 2018
Running a sequence item in sequence and sequencer UVM UVM , sequence , sequence-and-sequencer	6	11601	April 28, 2018
What is the meaning of this following sequence? SystemVerilog SystemVerilog , assertion , sequence	3	1423	February 26, 2018
Is it not possible to use sample functions like $fell in Sequence in assertions? SystemVerilog SystemVerilog , assertion , sequence , fell , Sample-function , throughout	2	1708	January 18, 2018
Using sequence to capture protocol violations SystemVerilog SystemVerilog , sequence , assert , actual-interface	2	1267	January 2, 2018
How To Know Which Sequence is Currently Running? OVM OVM , sequence , current-running-sequence	1	2040	March 7, 2017
When writing to a field in a register in Config seq vs other sequnces UVM UVM , Write , virtual-sequence , sequence , config , config-sequence	0	1462	February 3, 2017
ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles SystemVerilog SystemVerilog , sequence , Signal-Relation , Repeat-Untill , Use-of-1-repeat-until	8	2423	August 31, 2016
Selecting a sequence in controlled form from large number of sequences..? UVM UVM , sequence , sequence_library	6	1976	June 26, 2016
Stoping a sequencer and starting it again in UVM UVM UVM , sequence , sequncer	13	9017	June 16, 2016
How do I create a pipelined Driver Sequencer REQ and RSP channel? UVM UVM , sequence , REQ , RSP , Pipelined	3	5951	January 26, 2016
Randomizing a UVM_SEQUENCE using a config object from the sequencer upon which it will be run UVM UVM , sequence , UVM-Configuration-database	8	9185	November 16, 2015
Sequence start from test in UVM UVM UVM , sequence , sequencer-test-uvm	1	2578	June 9, 2015
Two sequences communication UVM UVM , sequence , sequence-item	2	2030	May 6, 2015
Sequence UVM UVM , sequence	1	1661	February 23, 2015
Stucking with sequence of sequences UVM UVM , configuration , sequence	1	1905	January 28, 2015
Why cant we run same sequence in multiple sequencer ? I want the perfect reason For that? UVM UVM , sequence	1	4178	September 8, 2014
How to build a relationship between different sequences? UVM UVM , sequence , uvm_driver , multiple-interface	5	2480	May 26, 2014
SV sequence as event control SystemVerilog SystemVerilog , System-Verilog , virtual-interface , sequence	1	1907	April 12, 2014
Sequences Priority/Arbitration UVM UVM , sequence , Arbitration , Priority	1	2263	April 3, 2014
Sequence not scheduling on a proper sequencer UVM UVM , sequence , sequencer-agents	1	1618	March 1, 2014