Using sequence to capture protocol violations

SystemVerilog
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1

Hi all,

I created this interface with an assert that checks that a valid e1_num is a periodic counter range in [0:N-1]:


interface e1_if #(parameter N = 5)(input clock);
	logic [7:0] 			data;
	logic				valid;
	logic [common::log2(N)-1:0]	e1_num;
	// this 2 lines exists just to support the assert below
	logic [common::log2(N)-1:0]		prev_e1_num = 0;
	always @(posedge clock) if(valid) 	prev_e1_num <= e1_num;

	property non_consequtive_e1_num;
		@(posedge clock) valid |-> if (e1_num != 0) (e1_num - prev_e1_num == 1)
			else (e1_num - prev_e1_num == -(N-1));
	endproperty

	ERROR_non_consequtive_e1_num: assert property (non_consequtive_e1_num);
endinterface

I want to use sequence block to describe the expected behavior instead of using the support signal prev_e1_num. Any idea how to write it?
I want to write a sequence that describe two consequtive valid with e1_num incremented by 1.

2

In reply to yakirmishli:

I want to use sequence block to describe the expected behavior instead of using the support signal prev_e1_num. Any idea how to write it?

What’s wrong in using support logic, as long as your assertion is correct?

I want to write a sequence that describes two consecutive valid with e1_num incremented by 1.


logic				valid;
logic [common::log2(N)-1:0]	e1_num;
sequence q_really_consecutive; 
 valid[*2] ##0 e1_num==$past(e1_num -1'b1);
endsequence

sequence q_sparcely_consecutive; 
  logic [common::log2(N)-1:0]	v_e1;
  (valid, v_e1==e1_num) ##1 valid[->1] ##0 e1_num==v_e1 -1'b1);
endsequence

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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3

In reply to ben@SystemVerilog.us:

What’s wrong in using support logic, as long as your assertion is correct?

Nothing. I just started to learn the sequence style and wanted to use it. I want to believe that when I be skilled enough it will be more productive than RTL logic for debug.

Thanks for the example - exactly what I tried to do :-)